Stochastic Process Variation in Deep-Submicron CMOS

Stochastic Process Variation in Deep-Submicron CMOS
Author :
Publisher : Springer Science & Business Media
Total Pages : 207
Release :
ISBN-10 : 9789400777811
ISBN-13 : 9400777817
Rating : 4/5 (11 Downloads)

Book Synopsis Stochastic Process Variation in Deep-Submicron CMOS by : Amir Zjajo

Download or read book Stochastic Process Variation in Deep-Submicron CMOS written by Amir Zjajo and published by Springer Science & Business Media. This book was released on 2013-11-19 with total page 207 pages. Available in PDF, EPUB and Kindle. Book excerpt: One of the most notable features of nanometer scale CMOS technology is the increasing magnitude of variability of the key device parameters affecting performance of integrated circuits. The growth of variability can be attributed to multiple factors, including the difficulty of manufacturing control, the emergence of new systematic variation-generating mechanisms, and most importantly, the increase in atomic-scale randomness, where device operation must be described as a stochastic process. In addition to wide-sense stationary stochastic device variability and temperature variation, existence of non-stationary stochastic electrical noise associated with fundamental processes in integrated-circuit devices represents an elementary limit on the performance of electronic circuits. In an attempt to address these issues, Stochastic Process Variation in Deep-Submicron CMOS: Circuits and Algorithms offers unique combination of mathematical treatment of random process variation, electrical noise and temperature and necessary circuit realizations for on-chip monitoring and performance calibration. The associated problems are addressed at various abstraction levels, i.e. circuit level, architecture level and system level. It therefore provides a broad view on the various solutions that have to be used and their possible combination in very effective complementary techniques for both analog/mixed-signal and digital circuits. The feasibility of the described algorithms and built-in circuitry has been verified by measurements from the silicon prototypes fabricated in standard 90 nm and 65 nm CMOS technology.


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